Finfet having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins

ABSTRACT

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T 1  of the cap portion is greater than a thickness T 2  of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. ApplicationSerial No. 16/942,781, filed on Jul. 30, 2020, now allowed. The entiretyof the above-mentioned patent application is hereby incorporated byreference herein and made a part of this specification.

BACKGROUND

As the semiconductor devices keep scaling down in size,three-dimensional multigate structures, such as the fin-type fieldeffect transistor (FinFET), have been developed to replace planar CMOSdevices. A characteristic of the FinFET device lies in that thestructure has one or more silicon-based fins that are wrapped around bythe gate to define the channel of the device. The gate wrappingstructure further provides better electrical control over the channel.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is an exemplary flow chart showing the process steps of a methodof fabricating a semiconductor device in accordance with someembodiments of the present disclosure.

FIGS. 2 to 12B are the perspective views and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some embodiments of the disclosure.

FIGS. 13 to 16B are the perspective and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some other embodiments of the disclosure.

FIGS. 17 to 21B are the perspective and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some other embodiments of the disclosure.

FIGS. 22 to 25 are the perspective views illustrating various stages ofa method of fabricating semiconductor devices in accordance with someother embodiments of the disclosure.

FIGS. 26 to 29 are the perspective and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some other embodiments of the disclosure.

FIG. 30 is a cross-sectional view illustrating a semiconductor device inaccordance with some alternative embodiments of the disclosure.

FIG. 31 is a cross-sectional view illustrating a semiconductor device inaccordance with some alternative embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature’s relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The fins may be patterned by any suitable method. For example, the finsmay be patterned using one or more photolithography processes, includingdouble-patterning or multi-patterning processes. Generally,double-patterning or multi-patterning processes combine photolithographyand self-aligned processes, allowing patterns to be created that have,for example, pitches smaller than what is otherwise obtainable using asingle, direct photolithography process. For example, in one embodiment,a sacrificial layer is formed over a substrate and patterned using aphotolithography process. Spacers are formed alongside the patternedsacrificial layer using a self-aligned process. The sacrificial layer isthen removed, and the remaining spacers may then be used to pattern thefins.

The embodiments of the present disclosure describe the exemplarymanufacturing processes of a three-dimensional structure with heightdifferences and the structure(s) fabricated there-from. Certainembodiments of the present disclosure describe the exemplarymanufacturing processes of fin field-effect transistor (FinFET) devicesand the FinFET devices fabricated there-from. The FinFET device may beformed on a monocrystalline semiconductor substrate, such as a bulksilicon substrate in certain embodiments of the present disclosure. Insome embodiments, the FinFET device may be formed on asilicon-on-insulator (SOI) substrate or a GOI (germanium-on-insulator)substrate as alternatives. Also, in accordance with the embodiments, thesilicon substrate may include other conductive layers, doped regions orother semiconductor elements, such as transistors, diodes or the like.The embodiments are intended to provide further explanations but are notused to limit the scope of the present disclosure.

FIG. 1 is an exemplary flow chart showing the process steps of a methodof fabricating a semiconductor device in accordance with someembodiments of the present disclosure. The various process steps of theprocess flow illustrated in FIG. 1 may comprise multiple process stepsas discussed below. FIG. 2 to FIG. 12B are the perspective views andcross-sectional views illustrating various stages of a method offabricating semiconductor devices in accordance with some embodiments ofthe disclosure. It is to be noted that the process steps describedherein cover a portion of the manufacturing processes used to fabricatea semiconductor device, such as a FinFET device.

FIG. 2 is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. In step S10 in FIG. 1 and asshown in FIG. 2 , a semiconductor substrate 200 is provided. In oneembodiment, the semiconductor substrate 200 comprises a crystallinesilicon substrate (e.g., wafer). The semiconductor substrate 200 maycomprise various doped regions depending on design requirements (e.g.,p-type semiconductor substrate or n-type semiconductor substrate). Insome embodiments, the doped regions may be doped with p-type or n-typedopants. For example, the doped regions may be doped with p-typedopants, such as boron or BF2; n-type dopants, such as phosphorus orarsenic; and/or combinations thereof. The doped regions may beconfigured for an n-type FinFET, or alternatively configured for ap-type FinFET. In some alternative embodiments, the semiconductorsubstrate 200 may be made of some other suitable elementalsemiconductor, such as diamond or germanium; a suitable compoundsemiconductor, such as gallium arsenide, silicon carbide, indiumarsenide, or indium phosphide; or a suitable alloy semiconductor, suchas silicon germanium carbide, gallium arsenic phosphide, or galliumindium phosphide.

In one embodiment, a pad layer 202 a and a mask layer 202 b aresequentially formed on the semiconductor substrate 200. The pad layer202 a may be a silicon oxide thin film formed, for example, by thermaloxidation process. The pad layer 202 a may act as an adhesion layerbetween the semiconductor substrate 200 and the mask layer 202 b. Thepad layer 202 a may also act as an etch stop layer for etching the masklayer 202 b. In at least one embodiment, the mask layer 202 b is asilicon nitride layer formed, for example, by low-pressure chemicalvapor deposition (LPCVD) or plasma enhanced chemical vapor deposition(PECVD). The mask layer 202 b is used as a hard mask during subsequentphotolithography processes. In certain embodiments, a patternedphotoresist layer 204 having a predetermined pattern is formed on themask layer 202 b.

FIG. 3 is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. In step S10 in FIG. 1 and asshown in FIG. 3 , the substrate 200 is patterned to form trenches 206 inthe substrate 200 and fins 208 are formed between the trenches 206. Forexample, the mask layer 202 b and the pad layer 202 a which are notcovered by the patterned photoresist layer 204 are sequentially etchedto form a patterned mask layer 202 b′ and a patterned pad layer 202 a′so as to expose the underlying semiconductor substrate 200. By using thepatterned mask layer 202 b′, the patterned pad layer 202 a′ and thepatterned photoresist layer 204 as a mask, portions of the semiconductorsubstrate 200 are exposed and etched to form the trenches 206 and thesemiconductor fins 208. In some embodiments, the semiconductor fins 208are covered by the patterned mask layer 202 b′, the patterned pad layer202 a′ and the patterned photoresist layer 204. Two adjacent trenches206 are spaced apart by a spacing. For example, the spacing betweentrenches 206 may be smaller than about 30 nm. In other words, twoadjacent trenches 206 are spaced apart by a corresponding semiconductorfin 208. The number of the fins 208 shown in FIG. 3 is merely forillustration, in some alternative embodiments, two or more parallelsemiconductor fins may be formed in accordance with actual designrequirements.

In some embodiments, a height of the semiconductor fins 208 and thedepth of the trench 206 range from about 5 nm to about 500 nm. After thetrenches 206 and the semiconductor fins 208 are formed, the patternedphotoresist layer 204 is then removed. In one embodiment, a cleaningprocess may be performed to remove a native oxide of the semiconductorsubstrate 200 a and the semiconductor fins 208. The cleaning process maybe performed using diluted hydrofluoric (DHF) acid or other suitablecleaning solutions.

FIG. 4 and FIG. 5 are perspective views of the semiconductor device atone of various stages of the manufacturing method. In step S12 in FIG. 1and as shown in FIG. 4 to FIG. 5 , a plurality of insulators 210 a areformed in the trenches 206 of the semiconductor substrate 200 a. Asillustrated in FIG. 4 , in some embodiments, an insulating material 210is first formed over the semiconductor substrate 200 a to cover thesemiconductor fins 208 and to fill up the trenches 206. Besides coveringthe semiconductor fins 208, the insulating material 210 is also coveringthe patterned pad layer 202 a′ and the patterned mask layer 202 b′. Insome embodiments, the insulating material 210 may include silicon oxide,silicon nitride, silicon oxynitride, a spin-on dielectric material, or alow-K dielectric material. It should be noted that the low-K dielectricmaterials are generally dielectric materials having a dielectricconstant lower than 3.9. The insulating material 210 may be formed byhigh-density-plasma chemical vapor deposition (HDP-CVD), sub-atmosphericchemical vapor deposition (SACVD) or by spin-on processes.

Referring to FIG. 5 , after forming the insulating material 210, etchingprocesses are performed to remove a portion of the insulating material210, the patterned mask layer 202 b′ and the patterned pad layer 202 a′until the semiconductor fins 208 are exposed. In some embodiments, theinsulating material 210 filled in the trenches 206 is partially removedby the etching process such that the insulators 210 a are formed on thesemiconductor substrate 200 a. For example, each insulator 210 a islocated between two adjacent semiconductor fins 208. In one embodiment,the etching process may be a wet etching process with hydrofluoric acid(HF) or a dry etching process. In some embodiments, the top surfaces201T of the insulators 210 a are lower than the top surfaces 208T of thesemiconductor fins 208. The semiconductor fins 208 protrude from the topsurfaces 201T of the insulators 210 a. The height difference between thetop surfaces 208T of the semiconductor fins 208 and the top surfaces201T of the insulators 210 a ranges from about 15 nm to about 50 nm. Insome embodiments, the protruded portions of the semiconductor fins 208include a channel region 208A and source/drain regions 208B locatedaside the channel region 208A. In certain embodiments, the source/drainregions 208B of the semiconductor fins 208 are of substantially the sameheight as that of the channel region 208A of the fins 208.

FIG. 6A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 6B is a sectional viewillustrating the semiconductor device of FIG. 6A taken along the lineA-A′. In step S14 in FIG. 1 and as shown in FIG. 6A and FIG. 6B, a linerstructure 212 is formed on the plurality of insulators 210 a and acrossthe semiconductor fins 208. In the exemplary embodiment, the linerstructure 212 includes a cap portion 212A, sidewall portions 212B andbase portions 212C. The cap portion 212A is covering the top surfaces208T of the semiconductor fins 208 and joined with the sidewall portions212B. The sidewall portions 212B are covering sidewalls 208SD of thesemiconductor fins 208. In some embodiments, the sidewall portions 212Bmay include a first sidewall portion 212B-1 and a second sidewallportion 212B-2 covering opposite sidewalls 208SD of a semiconductor fin208. The cap portion 212A may be joining the first sidewall portion212B-1 to the second sidewall portion 212B-2. Furthermore, the baseportions 212C are covering the insulators 210 a and joined with thesidewall portions 212B. For example, the base portions 212C may bejoined with the first sidewall portion 212B-1 and/or the second sidewallportion 212B-2.

As illustrated in FIG. 6A and FIG. 6B, a maximum thickness of the capportion 212A is T₁, a thickness of the sidewall portions 212B is T₂, anda thickness of the base portions 212C is T₃. In some embodiments, themaximum thickness T₁ of the cap portion 212A is greater than thethickness T₂ of the sidewall portions 212B. In some embodiments, themaximum thickness T₁ and the thickness T₂ satisfies the relationship:0.08 ≤ [(T₁-T₂)/T₂] ≤ 0.26. Furthermore, the thickness T₃ of the baseportions 212C is substantially equal to the thickness T₂ of the sidewallportions 212B. In the exemplary embodiment, by controlling thethicknesses of the cap portion 212A, the sidewall portions 212B and thebase portions 212C T₁, T₂ and T₃ in such a range, an issue ofover-etching on the semiconductor fins 208 or the formation of pits onthe semiconductor fins 208 may be prevented. In some embodiments, if[(T₁-T₂)/T₂] is smaller than 0.08, then the impact on the formation ofpits on the semiconductor fins 208 becomes worse. In some otherembodiments, if [(T₁-T₂)/T₂] is greater than 0.26, then it increases themanufacturing time during subsequent etching process, and increases themanufacturing cost.

In the exemplary embodiment, the liner structure 212 is formed byperforming a deposition process and a plasma treatment process, forexample. In some embodiments, the deposition process includesintroducing a plurality of precursors over a surface of the plurality ofinsulators 210 a and on the semiconductor fins 208 to form a liner layer(not shown). In certain embodiments, the deposition process is aplasma-enhanced atomic layer deposition (PEALD) process, and theplurality of precursors is silicon-containing precursors. In oneembodiment, the silicon-containing precursors is SAM-24(H₂Si[N(C₂H₅)₂]₂). Furthermore, in some embodiments, the plasma-enhancedatomic layer deposition process may be performed at a plasma power of 15W to 800 W. In certain embodiments, the plasma-enhanced atomic layerdeposition process may be performed at a plasma power of 500 W to 650 Wto form the liner layer. The plasma-enhanced atomic layer depositionprocess is performed at a plasma power of 500 W to 650 W so that theliner layer having the desired thickness is ensured. In one embodiment,the plasma-enhanced atomic layer deposition process may be performed ata plasma power of 600 W.

Moreover, in some embodiments, the plasma treatment process includestreating the liner layer with a plasma selected from the groupconsisting of helium, argon, oxygen and hydrogen for 20 to 40 secondsunder a source power of 500 W to 1500 W to form the liner structure 212.In some embodiments, the plasma treatment process includes a decoupledplasma oxidation process to form an oxide layer (e.g. such as siliconoxide) constituting the liner structure 212. In some embodiments, theplasma treatment process is performed to increase the thickness of thecap portion 212A of the liner structure 212. In other words, after theplasma treatment process, the liner structure 212 including the capportion 212A, the sidewall portions 212B, and the base portions 212C maybe formed.

FIG. 7A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 7B is a sectional viewillustrating the semiconductor device of FIG. 7A taken along the lineB-B′. In step S16 in FIG. 1 and as shown in FIG. 7A and FIG. 7B, adielectric layer 214 is conformally formed over the liner structure 212and across the semiconductor fins 208. In some embodiments, a thicknessof the dielectric layer 214 is maintained to be the same along the baseportions 212C, the sidewall portions 212B and the cap portion 212A ofthe liner structure 212. In other words, a thickness of the dielectriclayer 214 on the sidewall portions 212B is the same as a thickness ofthe dielectric layer 214 on the cap portion 212A. In certainembodiments, the dielectric layer 214 is formed to cover the channelregion 208A and the source/drain regions 208B of the semiconductor fins208. In some embodiments, the liner structure 212 is sandwiched inbetween the insulators 210 a and the dielectric layer 214, or sandwichedin between the semiconductor fins 208 and the dielectric layer 214. Insome embodiments, the material of the dielectric layer 214 may besilicon oxide, silicon nitride, silicon carbonitride or the like. Insome embodiments, the method of forming the dielectric layer 214 may bean atomic layer deposition method. In some alternative embodiments, theformation of a dielectric layer 214 on the insulators 210 a may beomitted.

FIG. 8 is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. In step S18 in FIG. 1 and asshown in FIG. 8 , a dummy gate stack 216 is formed on the dielectriclayer 214 and across the semiconductor fins 208. The dummy gate stack216 may include a polysilicon strip 216A and a hard mask strip 216B. Insome embodiments, the dummy gate stack 216 is formed by forming a dummylayer (including a polysilicon layer and a hard mask layer) over thedielectric layer 214 and across the semiconducfigtor fins 208, andpatterning the dummy layer to form the polysilicon strip 216A and thehard mask strip 216B. In the exemplary embodiment, although one dummygate stack 216 is illustrated herein, it should be noted that the numberof dummy gate stack 216 is not limited to one and may be more than one.In some embodiments, the extension direction of the dummy gate stack 216(the polysilicon strip 216A and the hard mask strip 216B) is arranged tobe perpendicular to the extension direction of the semiconductor fins208, and the dummy gate stack 216 is arranged across the semiconductorfins 208 and covers the channel region 208A of the semiconductor fins208. In one embodiment, the material of the hard mask strip 216Bincludes silicon nitride, silicon oxide or the combination thereof.

Referring still to FIG. 8 , after forming the dummy gate stack 216,spacer structures 218 are formed on two opposite sides of the dummy gatestack 216. In some embodiments, the spacer structures 218 are located onthe dielectric layer 214 and are covering sidewalls of the polysiliconstrip 216A and the hard mask strip 216B. In some embodiments, the spacerstructures 218 may be formed by conformally forming a spacer materiallayer over the dielectric layer 214 and over the dummy gate stack 216,then performing an etching process on the spacer material layer to formthe spacer structures 218. In some embodiments, the spacer materiallayer is formed of one or more dielectric materials, such as siliconnitride, silicon carbon oxynitride (SiCON), silicon carbonitride (SiCN)or combinations thereof. The spacer material layer may be a single layeror a multilayered structure. In some embodiments, the spacer materiallayer is formed by depositing a blanket layer of one or more dielectricmaterials. In one embodiment, the spacer material layer has a thicknessranging from 3 nm to 10 nm.

FIG. 9A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 9B is a sectional viewillustrating the semiconductor device of FIG. 9A taken along the lineC-C′. Referring to FIG. 9A and FIG. 9B, after forming the dummy gatestack 216 and the spacer structures 218, the dielectric layer 214 ispatterned so that side surfaces 214SD of the dielectric layer 214 arealigned with side surfaces of the spacer structure 218. In someembodiments, portions of the dielectric layer 214 not covered by thedummy gate stack 216 and the spacer structures 218 are removed. Incertain embodiments, the dielectric layer 214 may be patterned orremoved by, for example, anisotropic etching, isotropic etching, and/orthrough atomic layer etching (ALE) processes.

Referring to FIG. 9A and FIG. 9B, on the channel region 208A (see FIG. 5) of the semiconductor fins 208, the liner structure 212 still includesthe cap portion 212A, sidewall portions 212B and the base portions 212C,wherein the cap portion 212A has the greatest thickness T₁. In someembodiments, portions of the liner structure 212 located on thesource/drain regions 208B (see FIG. 5 ) of the semiconductor fins 208may be patterned and removed along with the dielectric layer 214. Forexample, after the patterning process, the cap portion 212A, thesidewall portions and the base portions 212C of the liner structure 212located on the source/drain regions 208B are removed. In other words,the liner structure 212 on the source/drain regions 208B may be removedby selective etching processes to reveal the semiconductor fins 208. Incertain embodiments, side surfaces 212SD of the liner structure 212 maybe aligned with the side surfaces 214SD of the dielectric layer 214after the patterning process.

FIG. 10 is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. In step S20 in FIG. 1 and asshown in FIG. 10 , strained material portions 220 may be formed on thesource/drain regions 208B (see FIG. 5 ) of the semiconductor fins 208.In some embodiments, the strained material portions 220 are formed overportions of the semiconductor fins 208 that are revealed by the dummygate stack 216. In some embodiments, the strained material portions 220covers and contacts the semiconductor fins 208. In some embodiments, thestrained material portions 220 are located on two opposite sides of thedummy gate stack 216.

In the exemplary embodiment, the strained material portions 220 (or ahigh doped low resistance material) is grown on the source/drain regions208B of the semiconductor fins 208 to strain or stress the semiconductorfins 208. Thus, the strained material portions 220 comprises a sourcedisposed at a side of the dummy stack gate 216 and a drain disposed atthe other side of the dummy gate stack 216. The source covers an end ofthe semiconductor fins 208 and the drain covers the other end of thesemiconductor fins 208. In some embodiments, the strained materialportions 220 may be doped with a conductive dopant. In one embodiment,the strained material portions 220 include materials such as SiGe, andis epitaxial-grown with a p-type dopant for straining a p-type FinFET.That is, the strained material portions 220 is doped with the p-typedopant to be the source and the drain of the p-type FinFET. The p-typedopant comprises boron or BF₂, and the strained material portions 220may be epitaxial-grown by LPCVD process with in-situ doping. In anotherembodiment, the strained material portions 220 include materials such asSiC, SiP, a combination of SiC/SiP, or SiCP, and is epitaxial-grown withan n-type dopant for straining an n-type FinFET. That is, the strainedmaterial portions 220 is doped with the n-type dopant to be the sourceand the drain of the n-type FinFET. The n-type dopant comprises arsenicand/or phosphorus, and the strained material portions 220 may beepitaxial-grown by LPCVD process with in-situ doping. The strainedmaterial portions 220 may be a single layer or a multi-layer.

FIG. 11 is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. In step S22 in FIG. 1 and asshown in FIG. 11 , an interlayer dielectric layer 222 is formed on theinsulators 210 a and covering the strained material portions 220. Insome embodiments, the interlayer dielectric layer 222 is formed adjacentto the spacer structures 218. In some embodiments, the interlayerdielectric layer 222 includes silicon oxide, silicon nitride, siliconoxynitride, phosphosilicate glass (PSG), borophosphosilicate glass(BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbondoped silicon oxide (e.g., SiCOH), polyimide, and/or a combinationthereof. In some other embodiments, the interlayer dielectric layer 222includes low-K dielectric materials. Examples of low-K dielectricmaterials include BLACK DIAMOND® (Applied Materials of Santa Clara,Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB(bis-benzocyclobutenes), Flare, SILK® (Dow Chemical, Midland, Mich.),hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF),and/or a combination thereof. It is understood that the interlayerdielectric layer 222 may include one or more dielectric materials and/orone or more dielectric layers.

In some embodiments, the interlayer dielectric layer 222 is formed to asuitable thickness by flowable CVD (FCVD), CVD, high density plasma CVD(HDPCVD), sub-atmospheric CVD (SACVD), spin-on, sputtering, or othersuitable methods. Specifically, an interlayer dielectric material layer(not illustrated) is formed to cover the insulators 210 a and the dummygate stack 216 first. Subsequently, the thickness of the interlayerdielectric material layer is reduced until a top surface of the dummygate stack 216 is exposed, so as to form the interlayer dielectric layer222. The process of reducing the thickness of the interlayer dielectricmaterial layer is achieved by a chemical mechanical polishing (CMP)process, an etching process, or other suitable process. The disclosureis not limited thereto.

FIG. 12A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 12B is a sectional viewillustrating the semiconductor device of FIG. 12A taken along the lineD-D′. In step S24 in FIG. 1 and as shown in FIG. 12A and FIG. 12B, agate stack 224 is formed by replacing the dummy gate stack 216 with thegate stack 224. In some embodiments, the polysilicon strip 216A and thehard mask strip 216B located on the channel region 208A of thesemiconductor fins 208 are removed. In one embodiment, the polysiliconstrips 216A and the hard mask strips 216B are removed by anisotropicetching, whereas the spacer structures 218, the liner structure 212 andthe dielectric layer 214 are retained. After removing the dummy gatestack 216, a gate stack 224 is formed over the channel region 208A ofthe semiconductor fins 208, and over the liner structure 212 and on thedielectric layer 214.

As illustrated in FIG. 12A and FIG. 12B, the gate stack 224 includes agate dielectric layer 224A and a gate electrode layer 224B, and the gatestack 224 is located in between the spacer structures 218. In anembodiment, the gate dielectric layer 224A is formed within the recessesbetween the spacer structures 218 and on the dielectric layer 214, andover the channel regions 208A of the semiconductor fins 208. In someembodiments, the gate dielectric layer 224A is conformally formed on thedielectric layer 214 and over the liner structure 212. In someembodiments, a thickness of the gate dielectric layer 224A is maintainedto be the same along the base portions 212C, the sidewall portions 212Band the cap portion 212A of the liner structure 212.

In some embodiments, the material of the gate dielectric layer 224Aincludes silicon oxide, silicon nitride or the combination thereof. Insome embodiments, the gate dielectric layer 224A includes a high-kdielectric material, and the high-k dielectric material has a k valuegreater than about 3.9 and includes a metal oxide or a silicate of Hf,Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof. In someembodiments, the gate dielectric layer 224A is formed by atomic layereddeposition, molecular beam deposition (MBD), physical vapor deposition(PVD) or thermal oxidation. After forming the gate dielectric layer224A, the gate electrode layer 224B is formed on the gate dielectriclayer 224A, over the channel region 208A of the semiconductor fins 208and fills the remaining recesses between the spacer structures 218. Incertain embodiments, the gate dielectric layer 224A is formed in betweenthe gate electrode layer 224B and the dielectric layer 214.

In some embodiments, the gate electrode layer 224B includes ametal-containing material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl,TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof. Depending onwhether the semiconductor device is a p-type FinFET or an n-type FinFET,the materials of the gate dielectric layer 224A and/or the gateelectrode layer 224B are appropriately chosen. Optionally, a chemicalmechanical polishing (CMP) process is performed to remove the excessportions of gate dielectric layer 224A and the gate electrode layer224B. The spacer structures 218 are located on sidewalls of the gatedielectric layer 224A and the gate electrode layer 224B. In other words,the dummy gate stack 216 is replaced, and the gate stack 224 is formed.In some embodiments described herein, the gate stack 216 is areplacement metal gate, but the structure(s) of the gate stack(s) or thefabrication processes thereof are not limited by these embodiments. Upto here, a semiconductor device SM1 according to some embodiments of thepresent disclosure is accomplished.

FIG. 13 to FIG. 16B are perspective and sectional views illustratingvarious stages of a method of fabricating semiconductor devices inaccordance with some other embodiments of the disclosure. The embodimentshown in FIG. 13 to FIG. 16B is similar to the embodiment shown in FIG.2 to FIG. 12B, hence the same reference numerals are used to refer tothe same or like parts, and its detailed description will be omittedherein. The difference between the embodiments is that the dielectriclayer 214 is omitted.

In the exemplary embodiment, the same steps described in FIG. 2 to FIG.6B may be performed to form the liner structure 212 over the insulators210 a and across the semiconductor fins 208. Referring to FIG. 13 ,after forming the liner structure 212, a dummy gate stack 216 is formedon the liner structure 212 and across the semiconductor fins 208. Forexample, the dummy gate stack 216 covers the channel region 208A of thesemiconductor fins 208. Furthermore, spacer structures 218 are formedover the liner structure 212 on two opposite sides of the dummy gatestack 216.

Referring to FIG. 14 , in a next step, the liner structure 212 ispatterned so that side surfaces 212SD of the liner structure 212 arealigned with side surfaces of the spacer structure 218. In someembodiments, portions of the liner structure 212 not covered by thedummy gate stack 216 and the spacer structures 218 are removed. Incertain embodiments, the liner structure 212 may be patterned or removedby, for example, anisotropic etching, isotropic etching, and/or throughatomic layer etching (ALE) processes.

Referring to FIG. 15 , the same steps may be performed to form strainedmaterial portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby the strained material portions 220covers and contacts the semiconductor fins 208. Similarly, an interlayerdielectric layer 222 is formed on the insulators 210 a and covering thestrained material portions 220.

FIG. 16A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 16B is a sectional viewillustrating the semiconductor device of FIG. 16A taken along the lineE-E′. Referring to FIG. 16A and FIG. 16B, after forming the interlayerdielectric layer 222, the dummy gate stack 216 may be removed andreplaced with gate stack 224. As such, a semiconductor device SM2according to some other embodiments of the present disclosure isaccomplished. Referring to FIG. 16A and FIG. 16B, on the channel region208A (see FIG. 5 ) of the semiconductor fins 208, the liner structure212 still includes the cap portion 212A, sidewall portions 212B and thebase portions 212C. For example, the liner structure 212 is sandwichedin between the semiconductor fins 208 and the gate dielectric layer224A.

FIG. 17 to FIG. 21B are the perspective and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some other embodiments of the disclosure. Theembodiment shown in FIG. 13 to FIGS. 16 is similar to the embodimentshown in FIG. 2 to FIG. 12B, hence the same reference numerals are usedto refer to the same or like parts, and its detailed description will beomitted herein. The difference between the embodiments is in thematerial of the semiconductor fins 208.

Referring to FIG. 17 , the same steps described in FIG. 2 to FIG. 5 maybe performed to form the semiconductor fins 208, and insulators 210 a inbetween the semiconductor fins 208. In the previous embodiments, thesemiconductor fins 208 may be silicon fins, for example. However, thedisclosure is not limited thereto, and in FIG. 17 to FIG. 21B, thesemiconductor fins 208 are silicon-germanium (SiGe) fins, for example.In the exemplary embodiment, when the semiconductor fins 208 are silicongermanium fins, an additional capping layer 211 may be formed to coverthe semiconductor fins 208. In some embodiments, the capping layer 211may be a silicon capping layer. In some embodiments, the capping layer211 is formed over the semiconductor fins 208 by low-pressure chemicalvapor deposition (LPCVD) or plasma enhanced chemical vapor deposition(PECVD). For example, the capping layer 211 covers the top surfaces 208Tand sidewalls 208SD of the semiconductor fins 208. In some embodiments,the capping layer 211 (silicon capping layer) is used to prevent theoxidation on the semiconductor fins 208 during the formation of theliner structure 212 performed in a subsequent step. In certainembodiments, the capping layer 211 prevents the formation of silicongermanium oxide (SiGeOx), which may affect the mobility of thesemiconductor device.

Referring to FIG. 18 , after forming the capping layer 211, the samesteps described in FIG. 6A to FIG. 8 may be performed to form the linerstructure 212 over the capping layer 211, and to form the dielectriclayer 214 over the liner structure 212. Thereafter, a dummy gate stack216 and spacer structures 218 are formed on the dielectric layer 214,whereby the dummy gate stack 216 is located in between the spacerstructures 218.

FIG. 19A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 19B is a sectional viewillustrating the semiconductor device of FIG. 19A taken along the lineF-F′. Referring to FIG. 19A and FIG. 19B, after forming the dummy gatestack 216 and the spacer structures 218, the dielectric layer 214 ispatterned so that side surfaces 214SD of the dielectric layer 214 arealigned with side surfaces of the spacer structure 218. Similarly,portions of the liner structure 212 located on the source/drain regions208B (see FIG. 5 ) of the semiconductor fins 208 may be patterned andremoved along with the dielectric layer 214.

Referring to FIG. 19A and FIG. 19B, on the channel region 208A (see FIG.5 ) of the semiconductor fins 208, the liner structure 212 stillincludes the cap portion 212A, sidewall portions 212B and the baseportions 212C. Furthermore, in some embodiments, the capping layer 211may be retained on the source/drain regions 208B (see FIG. 5 ) of thesemiconductor fins 208. However, the disclosure is not limited thereto.For example, in some alternative embodiments, the capping layer 211 onthe source/drain regions 208B may be removed to reveal the semiconductorfins 208 before forming the strained material portions 220. Asillustrated in FIG. 19A and FIG. 19B, in some embodiments, the cappinglayer 211 is sandwiched in between the liner structure 212 and thechannel region 208A of the semiconductor fins 208. In certainembodiments, the liner structure 212 is sandwiched in between thecapping layer 211 and the dielectric layer 214.

Referring to FIG. 20 , the same steps may be performed to form strainedmaterial portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby the strained material portions 220covers and contacts the capping layer 211 (silicon capping layer).Similarly, an interlayer dielectric layer 222 is formed on theinsulators 210 a and covering the strained material portions 220.

FIG. 21A is a perspective view of the semiconductor device at one ofvarious stages of the manufacturing method. FIG. 21B is a sectional viewillustrating the semiconductor device of FIG. 21A taken along the lineG-G′. Referring to FIG. 21A and FIG. 21B, after forming the interlayerdielectric layer 222, the dummy gate stack 216 may be removed andreplaced with gate stack 224. As such, a semiconductor device SM3according to some other embodiments of the present disclosure isaccomplished. Referring to FIG. 21A and FIG. 21B, on the channel region208A (see FIG. 5 ) of the semiconductor fins 208, the liner structure212 still includes the cap portion 212A, sidewall portions 212B and thebase portions 212C. For example, the liner structure 212 is located inbetween the capping layer 211 and the gate stack 224. In certainembodiments, the liner structure 212 is sandwiched in between thecapping layer 211 and the dielectric layer 214.

FIG. 22 to FIG. 25 are the perspective views illustrating various stagesof a method of fabricating semiconductor devices in accordance with someother embodiments of the disclosure. The embodiment shown in FIG. 22 toFIG. 25 is similar to the embodiment shown in FIG. 2 to FIG. 12B, hencethe same reference numerals are used to refer to the same or like parts,and its detailed description will be omitted herein. The differencebetween the embodiments is in the way of patterning the liner structure212.

FIG. 22 is a stage of manufacturing a semiconductor device similar tothat described in FIG. 8 , whereby a dummy gate stack 216 and spacerstructures 218 are formed on the dielectric layer 214. Referring to FIG.23 , after forming the dummy gate stack 216 and the spacer structures218, the dielectric layer 214 is patterned so that side surfaces 214SDof the dielectric layer 214 are aligned with side surfaces of the spacerstructure 218. In some embodiments, portions of the liner structure 212located on the source/drain regions 208B (see FIG. 5 ) of thesemiconductor fins 208 may be patterned and removed along with thedielectric layer 214. For example, after the patterning process, theliner structure 212 includes the cap portion 212A located on thesource/drain regions 208B of the semiconductor fins 208, whereas thesidewall portions and the base portions 212C are removed. In certainembodiments, sidewalls of the fins 208 are also revealed after thepatterning process. In some embodiments, through the patterning oretching processes, a thickness of the cap portion 212A on thesource/drain regions 208B is also reduced. In the exemplary embodiment,since the cap portion 212A initially has a thickness greater than thatof the sidewall portions 212B and the base portions 212C, the capportion 212A may be retained on the semiconductor fins 208 after thepatterning/etching processes.

Referring to FIG. 23 , the same steps may be performed to form strainedmaterial portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby the cap portion 212A may be covered bythe strained material portions 220. In certain embodiments, the capportion 212A of the liner structure 212 is disposed over thesource/drain regions 208B of the semiconductor fins 208 and sandwichedin between the strained material portions 220 and the semiconductor fin208. Similarly, an interlayer dielectric layer 222 is formed on theinsulators 210 a and covering the strained material portions 220.Referring to FIG. 25 , after forming the interlayer dielectric layer222, the dummy gate stack 216 may be removed and replaced with gatestack 224. As such, a semiconductor device SM4 according to some otherembodiments of the present disclosure is accomplished.

FIG. 26 to FIG. 29 are the perspective and cross-sectional viewsillustrating various stages of a method of fabricating semiconductordevices in accordance with some other embodiments of the disclosure. Theembodiment shown in FIG. 26 to FIG. 29 is similar to the embodimentshown in FIG. 2 to FIG. 12B, hence the same reference numerals are usedto refer to the same or like parts, and its detailed description will beomitted herein. The difference between the embodiments is in the designof the semiconductor fins 208.

FIG. 26 is a stage of manufacturing a semiconductor device similar tothat described in FIG. 9A, whereby the liner structure 212 and thedielectric layer 214 are pattered so that their side surfaces (212SD /214SD) may be aligned with side surfaces of the spacer structure 218.Referring to FIG. 27 , after patterning the liner structure 212 and thedielectric layer 214, the semiconductor fins 208 exposed by the dummygate stack 216 and the spacer structures 218 are removed/recessed toform a plurality of recessed portions Rc. For example, portions of thesemiconductor fins 208 may be removed by, anisotropic etching, isotropicetching, or a combination thereof. In some embodiments, portions of thesemiconductor fins 208 are recessed below the top surfaces of theinsulators 210 a. In some embodiments, a depth of the recessed portionsRc is less than a thickness of the insulators 210 a. In other words, thesemiconductor fins 208 exposed by the dummy gate stack 216 and thespacer structures 218 are not entirely removed, and the remainingsemiconductor fins 208 located in the recessed portion Rc form thesource/drain regions of the semiconductor fins 208.

Referring to FIG. 28 , in a next step, strained material portions 220may be formed over the recessed portions Rc of the semiconductor fins208. In some embodiments, the strained material portions 220 extendsbeyond the top surfaces of the insulators 210 a. The strained materialportions 220 is similar to that described in FIG. 10 , thus its detaileddiscussion will be omitted herein. Referring to FIG. 29 , the same stepsmay be performed to form an interlayer dielectric layer 222 on theinsulators 210 a and covering the strained material portions 220.Subsequently, the dummy gate stack 216 may be removed and replaced withgate stack 224. As such, a semiconductor device SM5 according to someother embodiments of the present disclosure is accomplished.

FIG. 30 is a cross-sectional view illustrating a semiconductor device inaccordance with some alternative embodiments of the disclosure. Thesemiconductor device illustrated in FIG. 30 is similar to thesemiconductor device SM1 illustrated in FIG. 12B, hence the samereference numerals are used to refer to the same or like parts, and itsdetailed description will be omitted herein. The difference between theembodiments is in the design of the liner structure 212.

In the previous embodiments, the liner structure 212 is formed with acap portion 212A having a substantially planar top surface. However, thedisclosure is not limited thereto. Referring to FIG. 30 , the capportion 212A of the liner structure 212 has a curved top surface. In theexemplary embodiment, a tip of the cap portion 212A has the maximumthickness T₁, while a side of the cap portion 212A joined with the firstsidewall portion 212B-1 has thickness T₁₃, and another side of the capportion 212A joined with the second sidewall portion 212B-2 hasthickness T₁₂. The thicknesses T₁₂ and T₁₃ being smaller than thethickness T₁. In other words, a thickness of the liner structure 212increases from the first sidewall portion 212B-1 to the cap portion 212Aand decreases from the cap portion 212A to the second sidewall portion212B-2.

FIG. 31 is a cross-sectional view illustrating a semiconductor device inaccordance with some alternative embodiments of the disclosure. Thesemiconductor device illustrated in FIG. 31 is similar to thesemiconductor device SM1 illustrated in FIG. 12B and similar to thesemiconductor device illustrate in FIG. 30 , hence the same referencenumerals are used to refer to the same or like parts, and its detaileddescription will be omitted herein. The difference between theembodiments is in the design of the liner structure 212.

In the previous embodiments, the liner structure 212 is formed withsidewall portions 212B having substantially the same thickness along thesidewalls of the semiconductor fins 208. However, the disclosure is notlimited thereto. Referring to FIG. 22 , besides having a cap portion212A with the curved top surface, a side of the first sidewall portion212B-1 and the second sidewall portion 212B-2 joined with the baseportions 212C has a thickness T₂₁, and another side of the firstsidewall portion 212B-1 and the second sidewall portion 212B-2 joinedwith the cap portion 212A has a thickness T₂₃. The thickness T₂₁ beingsmaller than the thickness T₂, while the thickness T₂₃ is greater thanthe thickness T₂. In other words, in the exemplary embodiment, athickness of the liner structure 212 gradually increases from the baseportion 212C to the first sidewall portion 212B-1 and to the cap portion212A, and gradually decreases from the cap portion 212A to the secondsidewall portion 212B-2 and to the base portion 212C.

In the above-mentioned embodiments, since the morphology of the linerstructure is modified to include a cap portion with greater thickness,the liner structure may act to prevent over-etching on the semiconductorfins or the formation of pits on the semiconductor fins. Furthermore, insituations where the semiconductor fins need to be further recessed,over-etching of the semiconductor fins or uneven etching of thesemiconductor fins may be prevented when forming the recess. In otherwords, the strained material portion may be formed over thesemiconductor fins having more smooth and planar surfaces due to linerstructure protection. Overall, a semiconductor device having lessdefects and improved performance may be achieved.

In accordance with some embodiments of the present disclosure, asemiconductor device includes a substrate, a plurality of insulators, aliner structure and a gate stack. The substrate has fins and trenches inbetween the fins. The insulators are disposed within the trenches of thesubstrate. The liner structure is disposed on the plurality ofinsulators and across the fins, wherein the liner structure comprisessidewall portions and a cap portion, the sidewall portions is coveringsidewalls of the fins, the cap portion is covering a top surface of thefins and joined with the sidewall portions, and a maximum thickness T₁of the cap portion is greater than a thickness T₂ of the sidewallportions. The gate stack is disposed on the liner structure and acrossthe fins.

In accordance with some other embodiments of the present disclosure, asemiconductor device includes a substrate, insulators, a linerstructure, a gate stack and strained material portions. The substrateincludes at least one fin, wherein the fin comprises a channel regionand source/drain regions. The insulators are disposed on the substrateand located on two sides of the fin. The liner structure is disposed onthe insulators and over the channel region of the fin, wherein the linerstructure comprises a first sidewall portion, a second sidewall portionand a cap portion, the first sidewall portion and the second sidewallportion are covering sidewalls of the fin, the cap portion is covering atop surface of the fin and joining the first sidewall portion to thesecond sidewall portion, and a thickness of the liner structureincreases from the first sidewall portion to the cap portion anddecreases from the cap portion to the second sidewall portion. The gatestack is disposed on the liner structure and across the channel regionof the fin. The strained material portions are disposed on thesource/drain regions of the fin.

In accordance with yet another embodiment of the present disclosure, amethod of fabricating a semiconductor device is described. The methodincludes the following steps. A substrate is provided. The substrate ispatterned to form trenches in the substrate and fins between thetrenches. A plurality of insulators is formed in the trenches of thesubstrate. A liner structure is formed on the plurality of insulatorsand across the fin. The liner structure is formed by performing adeposition process and a plasma treatment process. The depositionprocess is performed by introducing a plurality of precursors over asurface of the plurality of insulators and on the fins to form a linerlayer. The plasma treatment process is performed on the liner layer toform the liner structure, wherein after the plasma treatment process,the liner structure is formed to include sidewall portions, baseportions and a cap portion, the sidewall portions are covering sidewallsof the fins, the cap portion is covering a top surface of the fins andjoined with the sidewall portions, the base portions are covering theplurality of insulators and joined with the sidewall portions, and amaximum thickness T₁ of the cap portion is greater than a thickness T₂of the sidewall portions. A gate stack is formed on the liner structureand across the fins.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A structure, comprising: a plurality ofsemiconductor fins; a liner structure disposed on the plurality ofsemiconductor fins, wherein the liner structure comprises sidewallportions and a cap portion, the sidewall portions is covering sidewallsof the plurality of semiconductor fins, and the cap portion is coveringa top surface of the plurality of semiconductor fins and joined with thesidewall portions; a dielectric layer conformally covering the linerstructure and across the plurality of semiconductor fins; and a gatedielectric layer disposed on the dielectric layer and a gate electrodelayer disposed on the gate dielectric layer.
 2. The structure accordingto claim 1, wherein a maximum thickness T₁ of the cap portion is greaterthan a thickness T₂ of the sidewall portions.
 3. The structure accordingto claim 1, further comprising spacer structures located on two sides ofthe gate dielectric layer, wherein side surfaces of the spacerstructures are aligned with side surfaces of the dielectric layer. 4.The structure according to claim 3, further comprising an interlayerdielectric layer covering the side surfaces of the spacer structures andthe side surfaces of the dielectric layer.
 5. The structure according toclaim 4, wherein a top surface of the interlayer dielectric layer isaligned with a top surface of the gate dielectric layer and a topsurface of the gate electrode layer.
 6. The structure according to claim1, further comprising a capping layer disposed in between the pluralityof semiconductor fins and the liner structure, wherein the capping layeris in direct contact with the plurality of semiconductor fins.
 7. Thestructure according to claim 1, wherein a thickness of the dielectriclayer is maintained to be the same along the sidewall portions and thecap portion of the liner structure.
 8. A structure, comprising: asubstrate comprising at least one fin, wherein the fin comprises a firstregion and a second region; a liner structure disposed on the firstregion of the fin; a dielectric layer disposed on the first region ofthe fin over the liner structure; a gate stack disposed on the firstregion of the fin over the dielectric layer; strained material portionsdisposed on the second region of the fin; and an interlayer dielectriclayer disposed over the substrate and covering the strained materialportions, wherein the interlayer dielectric layer is contacting sidesurfaces of the liner structure and side surfaces of the dielectriclayer.
 9. The structure according to claim 8, further comprising acapping layer disposed on the first region and the second region of thefin, wherein the liner structure is located in between the capping layerand the gate stack in the first region, and the strained materialportions are covering the capping layer in the second region.
 10. Thestructure according to claim 9, further comprising insulators disposedon the substrate and located below the liner structure, wherein theinsulators are in direct contact with the capping layer and the linerstructure.
 11. The structure according to claim 8, wherein the linerstructure comprises sidewall portions and a cap portion, the sidewallportions are covering sidewalls of the fin, and the cap portion iscovering a top surface of the fin and joined with the sidewall portions,and a maximum thickness T₁ of the cap portion is greater than athickness T₂ of the sidewall portions.
 12. The structure according toclaim 11, wherein the liner structure further includes base portionsdisposed over the substrate and joined with the sidewall portions,wherein a thickness T₃ of the base portions is substantially equal tothe thickness T₂ of the sidewall portions.
 13. The structure accordingto claim 8, further comprising spacer structure disposed on two sides ofthe gate stack, wherein the interlayer dielectric layer is covering sidesurfaces of the spacer structure.
 14. The structure according to claim13, wherein the side surfaces of the spacer structure are aligned withthe side surfaces of the liner structure and the side surfaces of thedielectric layer.
 15. A structure, comprising: a substrate comprisingsemiconductor fins, wherein the semiconductor fins include a top surfaceand side surfaces joined with the top surface; a liner structure, afirst dielectric layer, a second dielectric layer and a gate electrodesequentially disposed on the semiconductor fins covering the top surfaceand the side surfaces of the semiconductor fins, wherein a thickness ofthe liner structure on the top surface of the semiconductor fins isgreater than a thickness of the first dielectric layer and a thicknessof the second dielectric layer on the top surface of the semiconductorfins.
 16. The structure according to claim 15, wherein a thickness ofthe liner structure on the side surfaces of the semiconductor fins issmaller than the thickness of the liner structure on the top surface ofthe semiconductor fins.
 17. The structure according to claim 15, whereina thickness of the first dielectric layer on the side surfaces of thesemiconductor fins is equal to the thickness of the first dielectriclayer on the top surface of the semiconductor fins.
 18. The structureaccording to claim 15, further comprising a capping layer covering thesemiconductor fins and located underneath the liner structure.
 19. Thestructure according to claim 18, wherein a bottom surface of the cappinglayer is aligned with a bottom surface of the liner structure.
 20. Thestructure according to claim 18, further comprising insulators disposedon the substrate and located underneath the capping layer and the linerstructure.